| You are not Logged In! |
Public:Layout Standards
See ((Schematic Conventions))
These standards are currently being worked on to try and increase reliability and professionalism of board design.
- Traces shall never create 90-degree angle except where absolutely necessary
- Components will always be placed horizontally or vertically, never at an angle
- Space is set aside on boards to provide information about the board
- *Board name
- *Version
- *Blank box for serial number
- *ISC logo
- Component values (e.g. R=100ohms, C=20uF) can be on fabrication layer (doesn't need to be on the silkscreen)
- *When soldering, simply reference a schematic/BOM
- Put the Reference-Designator (Ref-Des) on top of the component lengthwise
- Component Placement
- *Top Side
- **Oftentimes components are ideally all placed on the top layer. This is to make soldering easier, although this is somewhat mitigated when there are through-hole (TH) components. Furthermore, after installation signals are easier to probe if they are on the same side, since the bottom is often covered or the chip secured.
- *Both
- **If space is a concern, placing components on both sides is a viable solution.
- Copper Pour
- *Copper pour minimum width of 0.1mm is too small, increase it to at least 0.2mm
- **0.254mm is a good choice, as it converts to 0.01inches
- Pad mask
- *If possible, decrease pad mask clearance so there is solder mask between all SMD pads of the same chip.
Recommended Dimensions
These are some dimensions you can enter into KiCad when defining cleareances and stuff. They have been selected based on Bay Area Circuit's (BAC's) standard design capabilities, which are similar to that of other fab houses. To use the industry terminology, they're dimensions for Low Density Interconnect (LDI) technology PCBs.
The preferred units at ISC are milimeters (mm), and all values will be given in mm.
Traces and Vias
These dimensions can be set in the Design Rules -> Design Rules dialog box. They're the recommended values for the default net class, and you will likely want to increase them for traces that will carry considerable amounts of current. Don't worry about the settings for microvias (µvias), as we don't use at ISC since they cost extra money to fabricate.
- Trace Clearance: 0.1mm
- Track Width: 0.2mm
- Via Diameter: 0.7mm
- Via Drill: 0.3mm
These values are minimum values, and can be increased. When increasing the via drill size, it is important to increase the via diameter as well, because the difference between the two must be greater than 0.3mm to meet BAC's 0.15mm minimum annular ring requirement. The picture below might illustrates what the different dimensions mean.
Copper Pours
Also known as copper planes, zones, or a ground plane, copper pours can greatly ease PCB layout and increase PCB performance. These values are set for each copper pour separately, although you can use the "export setting to other zones" button to change the settings of all other pours to match.
- Clearance: 0.2mm
- Minimum Width: 0.2mm
- Antipad Clearance: 0.2mm
- Spoke Width: 0.3mm
- Segments / 360º: 32
- Pad Connection: Thermal Relief
These are all minimum values, and they can be increased to meet the needs of your design. It's also worth noting that the settings that dictate how pads connect to pours can be overridden at a footprint level and at a pin level, if you want different pins to connect to the same zone differently.
Pads Mask Clearance
These settings control how the soldermask is spread on your board. Soldermask is the It is important to set them correctly, as soldermask is incredibly useful in making your PCB easy to solder. Soldermask is the green (or some other color) coating on the top and bottom of the PCB. Its purpose is to cover the copper on the PCB to prevent shorts and oxidation, as well as to repell solder so that solder stays where you want it to stay.
- Solder Mask Clearance: 0.1mm
- Solder Mask Min Width: 0.15mm
These values can be reduced slightly if you want to get some soldermask between pins of a tight-pitch IC.
Further Reading
Bay Area Circuits's standard capabilities.